1. Field of the Invention
The present invention relates to an electrical inspection substrate unit including a multi-layer ceramic substrate which realizes highly accurate mounting, on a surface layer thereof, of connecting terminals for electrical inspection of a silicon wafer, and which can expand or shrink in a manner similar to that of a silicon wafer having a circuit thereon, even in the case where inspection is conducted over a wide temperature range (−50° C. to 150° C.).
2. Description of Related Art
In recent years, in IC chip inspections, the inspections performed on a silicon wafer unit have been required frequently. Particularly, at present, in association with development of large silicon wafers, inspections must be taken for silicon wafers having a size of φ 300 mm (12 inches).
For electrical inspections of such a silicon wafer, a jig used for inspection must be provided with connecting terminals which come into contact with IC chips. Since such connecting terminals repeatedly come into contact with IC chips, the terminals are required to have high strength.
Recently, in electrical inspection of a silicon wafer, a silicon wafer having passed electrical inspection has been required to be certified as a known good die (KGD). In order for a silicon wafer to be certified as a KGD, the wafer must pass a burn-in test (screening inspection under thermal and electrical loading).
However, in the case where a conventional jig for electrical inspection of a silicon wafer (wafer-inspection jig/probe card) is used for inspection of a silicon wafer, when electrical inspection is carried out at different temperatures, due to a considerable difference in thermal expansion coefficient between the wafer-inspection jig and the silicon wafer, mismatch in size occurs between the jig and the wafer through thermal expansion at the temperatures, and thus connecting terminals of the jig fail to come into contact with pads on the wafer.
Therefore, it is important that the thermal expansion coefficient of such a wafer-inspection jig be matched to some extent with that of a silicon wafer.
Meanwhile, such a wafer-inspection jig is required to include an electrical inspection substrate unit formed of a ceramic substrate, from the viewpoint of securing adhesion strength (with respect to repeated contact) of connecting terminals formed on the electrical inspection substrate unit. However, due to variation in an amount of shrinkage during firing, a typical method for manufacturing such a ceramic substrate encounters difficulty in attaining a dimensional accuracy required for connection of connecting terminals to pads on a silicon wafer.
A constrained sintering process is a technique for manufacturing a ceramic substrate required to exhibit high dimensional accuracy. In the constrained sintering process, top and bottom surfaces of a green sheet are provided with ceramic sheets (restraint sheets) which do not sinter at a temperature at which the green sheet is fired, and shrinkage of the green sheet during firing in an X-Y direction (plane direction) is suppressed by virtue of the presence of the ceramic sheets (restraint sheets), whereby high dimensional accuracy is attained.
In view of the foregoing, hitherto, attempts have been made to attain a ceramic composition of low thermal expansion (see: Japanese Patent Application Laid-Open (kokai) No. S63-107095; Japanese Patent Application Laid-Open (kokai) No. 2006-232645; and Japanese Patent Application Laid-Open (kokai) No. 2006-284541), and a low-temperature-firable ceramic material exhibiting high dimensional accuracy (see: Japanese Patent No. 2617643).